l GND!
h Vdd!
clock Vdd! 1
vector A A3 A2 A1 A0
vector B B3 B2 B1 B0
vector OUT1 OUT1_3 OUT1_2 OUT1_1 OUT1_0
vector OUT2 OUT2_3 OUT2_2 OUT2_1 OUT2_0
vector S S3 S2 S1 S0
w OUT2 OUT1 B A S
V A 1011 0111 0110 0111
V B 0100 1001 0010 0011
V S 0000 0101 1010 1111
analyzer OUT2 OUT1 B A S
R