** SPICE file created for circuit ha ** Technology: scmos ** ** NODE: 0 = GND ** NODE: 1 = Vdd ** NODE: 2 = Error RLUMP0 100 101 62.0 RLUMP1 102 103 1431.0 M0 101 103 1 1 pfet L=2.0U W=4.0U RLUMP2 104 105 857.5 RLUMP3 100 106 62.0 M1 1 105 106 1 pfet L=2.0U W=4.0U RLUMP4 107 108 20.5 RLUMP5 102 109 1431.0 RLUMP6 100 110 62.0 M2 108 109 110 0 nfet L=2.0U W=4.0U RLUMP7 104 111 857.5 RLUMP8 107 112 20.5 M3 0 111 112 0 nfet L=2.0U W=4.0U RLUMP9 102 113 1431.0 RLUMP10 114 115 415.0 M4 1 113 115 1 pfet L=2.0U W=4.0U RLUMP11 114 116 415.0 RLUMP12 102 117 1431.0 M5 116 117 0 0 nfet L=2.0U W=4.0U RLUMP13 104 118 857.5 RLUMP14 119 120 456.0 M6 1 118 120 1 pfet L=2.0U W=4.0U RLUMP15 119 121 456.0 RLUMP16 104 122 857.5 M7 121 122 0 0 nfet L=2.0U W=4.0U RLUMP17 102 123 1431.0 RLUMP18 124 125 39.5 M8 1 123 125 1 pfet L=2.0U W=8.0U RLUMP19 104 126 857.5 RLUMP20 127 128 39.5 M9 1 126 128 1 pfet L=2.0U W=8.0U RLUMP21 124 129 39.5 RLUMP22 119 130 456.0 RLUMP23 131 132 279.0 M10 129 130 132 1 pfet L=2.0U W=8.0U RLUMP24 127 133 39.5 RLUMP25 114 134 415.0 RLUMP26 131 135 279.0 M11 133 134 135 1 pfet L=2.0U W=8.0U RLUMP27 131 136 279.0 RLUMP28 104 137 857.5 RLUMP29 138 139 18.0 M12 136 137 139 0 nfet L=2.0U W=8.0U RLUMP30 131 140 279.0 RLUMP31 119 141 456.0 RLUMP32 142 143 18.0 M13 140 141 143 0 nfet L=2.0U W=8.0U RLUMP33 138 144 18.0 RLUMP34 102 145 1431.0 M14 144 145 0 0 nfet L=2.0U W=8.0U RLUMP35 142 146 18.0 RLUMP36 114 147 415.0 M15 146 147 0 0 nfet L=2.0U W=8.0U C0 142 0 17F ** NODE: 142 = xor2_0/8_172_127# C1 138 0 17F ** NODE: 138 = xor2_0/8_92_127# C2 131 0 164F ** NODE: 131 = Q C3 124 0 18F ** NODE: 124 = xor2_0/8_172_26# C4 127 0 18F ** NODE: 127 = xor2_0/8_92_10# C5 119 0 57F ** NODE: 119 = xor2_0/inv_0/Z C6 114 0 57F ** NODE: 114 = xor2_0/inv_1/Z C7 1 0 159F ** NODE: 1 = Vdd! ** NODE: 0 = GND! C8 107 0 12F ** NODE: 107 = nand2_0/8_7_19# C9 100 0 30F ** NODE: 100 = C C10 104 0 45F ** NODE: 104 = A C11 102 0 81F ** NODE: 102 = B VCC 1 0 5 VIN0 102 0 PWL ( 0NS 0 50N 0 100N 5 150N 5 200N 0 250N 0 300N 5 350N 5 + 400NS 0 450N 0 500N 5 550N 5 600N 0 650N 0 700N 5 750N 5 ) + DC 0 VIN1 104 0 PWL ( 0NS 0 50NS 0 100NS 0 150NS 0 200NS 5 250NS 5 300NS 5 350NS 5 + 400NS 0 450NS 0 500NS 0 550NS 0 600NS 5 650NS 5 700NS 5 750SN 5 ) + DC 0 .MODEL pfet PMOS .MODEL nfet NMOS .TRAN 1NSEC 750NSEC .END