** SPICE file created for circuit dff ** Technology: scmos ** ** NODE: 0 = GND ** NODE: 1 = Vdd ** NODE: 2 = Error RLUMP0 100 101 302.0 RLUMP1 102 103 554.5 M0 1 101 103 1 pfet L=2.0U W=4.0U RLUMP2 102 104 554.5 RLUMP3 105 106 222.5 M1 104 106 1 1 pfet L=2.0U W=4.0U RLUMP4 107 108 495.5 RLUMP5 102 109 554.5 M2 1 108 109 1 pfet L=2.0U W=4.0U RLUMP6 110 111 20.5 RLUMP7 100 112 302.0 RLUMP8 102 113 554.5 M3 111 112 113 0 nfet L=2.0U W=4.0U RLUMP9 114 115 20.5 RLUMP10 105 116 222.5 RLUMP11 110 117 20.5 M4 115 116 117 0 nfet L=2.0U W=4.0U RLUMP12 107 118 495.5 RLUMP13 114 119 20.5 M5 0 118 119 0 nfet L=2.0U W=4.0U RLUMP14 100 120 302.0 RLUMP15 121 122 367.0 M6 120 122 1 1 pfet L=2.0U W=4.0U RLUMP16 123 124 574.0 RLUMP17 100 125 302.0 M7 1 124 125 1 pfet L=2.0U W=4.0U RLUMP18 126 127 20.5 RLUMP19 121 128 367.0 RLUMP20 100 129 302.0 M8 127 128 129 0 nfet L=2.0U W=4.0U RLUMP21 123 130 574.0 RLUMP22 126 131 20.5 M9 0 130 131 0 nfet L=2.0U W=4.0U RLUMP23 132 133 1007.5 RLUMP24 121 134 367.0 M10 1 133 134 1 pfet L=2.0U W=4.0U RLUMP25 121 135 367.0 RLUMP26 132 136 1007.5 M11 135 136 0 0 nfet L=2.0U W=4.0U RLUMP27 137 138 302.0 RLUMP28 107 139 495.5 M12 1 138 139 1 pfet L=2.0U W=4.0U RLUMP29 107 140 495.5 RLUMP30 141 142 222.5 M13 140 142 1 1 pfet L=2.0U W=4.0U RLUMP31 102 143 554.5 RLUMP32 107 144 495.5 M14 1 143 144 1 pfet L=2.0U W=4.0U RLUMP33 145 146 20.5 RLUMP34 137 147 302.0 RLUMP35 107 148 495.5 M15 146 147 148 0 nfet L=2.0U W=4.0U RLUMP36 149 150 20.5 RLUMP37 141 151 222.5 RLUMP38 145 152 20.5 M16 150 151 152 0 nfet L=2.0U W=4.0U RLUMP39 102 153 554.5 RLUMP40 149 154 20.5 M17 0 153 154 0 nfet L=2.0U W=4.0U RLUMP41 137 155 302.0 RLUMP42 132 156 1007.5 M18 155 156 1 1 pfet L=2.0U W=4.0U RLUMP43 123 157 574.0 RLUMP44 137 158 302.0 M19 1 157 158 1 pfet L=2.0U W=4.0U RLUMP45 159 160 20.5 RLUMP46 132 161 1007.5 RLUMP47 137 162 302.0 M20 160 161 162 0 nfet L=2.0U W=4.0U RLUMP48 123 163 574.0 RLUMP49 159 164 20.5 M21 0 163 164 0 nfet L=2.0U W=4.0U C0 159 0 12F ** NODE: 159 = nand2_0/8_7_19# C1 149 0 12F ** NODE: 149 = nand3_0/8_33_19# C2 145 0 12F ** NODE: 145 = nand3_0/8_49_19# ** NODE: 141 = ~SET C3 137 0 40F ** NODE: 137 = nand3_0/A C4 132 0 38F ** NODE: 132 = D C5 126 0 12F ** NODE: 126 = nand2_1/8_7_19# C6 123 0 21F ** NODE: 123 = CLOCK C7 121 0 47F ** NODE: 121 = inv_0/Z ** NODE: 0 = GND! C8 114 0 12F ** NODE: 114 = nand3_1/8_33_19# C9 110 0 12F ** NODE: 110 = nand3_1/8_49_19# C10 1 0 127F ** NODE: 1 = Vdd! C11 102 0 59F ** NODE: 102 = ~Q C12 107 0 56F ** NODE: 107 = Q ** NODE: 105 = ~RESET C13 100 0 40F ** NODE: 100 = nand3_1/A VCC 1 0 DC 5 VIN_SET~ 141 0 PWL (0 0 10NS 0 20NS 5 80NS 5) + DC 0 VIN_CLR~ 105 0 PWL (0 5 20NS 5 50NS 5 60NS 0 70NS 0 80NS 5) + DC 0 VIN_D 132 0 PWL (0 0 130NS 0 140NS 5 170NS 5 180NS 0) + DC 0 ** clock xtupaei sta 150NS kai 210NSEC VIN_CLK 123 0 PWL (0 0 140NS 0 150NS 5 160NS 5 170NS 0 200NS 0 210NS 5 220NS 5 230NS 0) + DC 0 .MODEL pfet PMOS .MODEL nfet NMOS .TRAN 1NSEC 230NSEC .END