** SPICE file created for circuit xnor
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 1006.5
RLUMP1 102 103 415.0
M0 1 101 103 1 pfet L=2.0U W=4.0U
RLUMP2 102 104 415.0
RLUMP3 100 105 1006.5
M1 104 105 0 0 nfet L=2.0U W=4.0U
RLUMP4 106 107 1012.5
RLUMP5 108 109 292.0
M2 1 107 109 1 pfet L=2.0U W=4.0U
RLUMP6 108 110 292.0
RLUMP7 106 111 1012.5
M3 110 111 0 0 nfet L=2.0U W=4.0U
RLUMP8 100 112 1006.5
RLUMP9 113 114 39.5
M4 1 112 114 1 pfet L=2.0U W=8.0U
RLUMP10 108 115 292.0
RLUMP11 116 117 39.5
M5 1 115 117 1 pfet L=2.0U W=8.0U
RLUMP12 113 118 39.5
RLUMP13 106 119 1012.5
RLUMP14 120 121 278.5
M6 118 119 121 1 pfet L=2.0U W=8.0U
RLUMP15 116 122 39.5
RLUMP16 102 123 415.0
RLUMP17 120 124 278.5
M7 122 123 124 1 pfet L=2.0U W=8.0U
RLUMP18 120 125 278.5
RLUMP19 108 126 292.0
RLUMP20 127 128 18.0
M8 125 126 128 0 nfet L=2.0U W=8.0U
RLUMP21 120 129 278.5
RLUMP22 106 130 1012.5
RLUMP23 131 132 18.0
M9 129 130 132 0 nfet L=2.0U W=8.0U
RLUMP24 127 133 18.0
RLUMP25 100 134 1006.5
M10 133 134 0 0 nfet L=2.0U W=8.0U
RLUMP26 131 135 18.0
RLUMP27 102 136 415.0
M11 135 136 0 0 nfet L=2.0U W=8.0U
C0 131 0 17F
** NODE: 131 = 8_172_127#
C1 127 0 17F
** NODE: 127 = 8_92_127#
C2 120 0 160F
** NODE: 120 = Z
C3 113 0 18F
** NODE: 113 = 8_172_26#
C4 116 0 18F
** NODE: 116 = 8_92_10#
C5 108 0 50F
** NODE: 108 = inv_0/Z
C6 106 0 59F
** NODE: 106 = A
** NODE: 0 = GND!
C7 102 0 57F
** NODE: 102 = inv_1/Z
C8 1 0 124F
** NODE: 1 = Vdd!
C9 100 0 60F
** NODE: 100 = B
VCC 1 0 5

VIN0 100 0 PWL (   0NS 0   50N 0  100N 5  150N 5  200N 0  250N 0  300N 5  350N 5
+                400NS 0  450N 0  500N 5  550N 5  600N 0  650N 0  700N 5  750N 5 )

VIN1 106 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )


.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 750NSEC
.END