** SPICE file created for circuit xor
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 62.0
RLUMP1 102 103 302.0
M0 101 103 1 1 pfet L=2.0U W=4.0U
RLUMP2 104 105 302.0
RLUMP3 100 106 62.0
M1 1 105 106 1 pfet L=2.0U W=4.0U
RLUMP4 107 108 20.5
RLUMP5 102 109 302.0
RLUMP6 100 110 62.0
M2 108 109 110 0 nfet L=2.0U W=4.0U
RLUMP7 104 111 302.0
RLUMP8 107 112 20.5
M3 0 111 112 0 nfet L=2.0U W=4.0U
RLUMP9 102 113 302.0
RLUMP10 114 115 566.0
M4 113 115 1 1 pfet L=2.0U W=4.0U
RLUMP11 116 117 691.0
RLUMP12 102 118 302.0
M5 1 117 118 1 pfet L=2.0U W=4.0U
RLUMP13 119 120 20.5
RLUMP14 114 121 566.0
RLUMP15 102 122 302.0
M6 120 121 122 0 nfet L=2.0U W=4.0U
RLUMP16 116 123 691.0
RLUMP17 119 124 20.5
M7 0 123 124 0 nfet L=2.0U W=4.0U
RLUMP18 114 125 566.0
RLUMP19 126 127 668.0
M8 125 127 1 1 pfet L=2.0U W=4.0U
RLUMP20 116 128 691.0
RLUMP21 114 129 566.0
M9 1 128 129 1 pfet L=2.0U W=4.0U
RLUMP22 130 131 20.5
RLUMP23 126 132 668.0
RLUMP24 114 133 566.0
M10 131 132 133 0 nfet L=2.0U W=4.0U
RLUMP25 116 134 691.0
RLUMP26 130 135 20.5
M11 0 134 135 0 nfet L=2.0U W=4.0U
RLUMP27 104 136 302.0
RLUMP28 114 137 566.0
M12 136 137 1 1 pfet L=2.0U W=4.0U
RLUMP29 126 138 668.0
RLUMP30 104 139 302.0
M13 1 138 139 1 pfet L=2.0U W=4.0U
RLUMP31 140 141 20.5
RLUMP32 114 142 566.0
RLUMP33 104 143 302.0
M14 141 142 143 0 nfet L=2.0U W=4.0U
RLUMP34 126 144 668.0
RLUMP35 140 145 20.5
M15 0 144 145 0 nfet L=2.0U W=4.0U
C0 140 0 12F
** NODE: 140 = nand2_0/8_7_19#
C1 130 0 12F
** NODE: 130 = nand2_1/8_7_19#
C2 126 0 24F
** NODE: 126 = A
C3 119 0 12F
** NODE: 119 = nand2_2/8_7_19#
C4 116 0 26F
** NODE: 116 = B
C5 114 0 51F
** NODE: 114 = nand2_2/A
** NODE: 0 = GND!
C6 107 0 12F
** NODE: 107 = nand2_3/8_7_19#
C7 100 0 32F
** NODE: 100 = Z
C8 1 0 101F
** NODE: 1 = Vdd!
C9 104 0 44F
** NODE: 104 = nand2_3/B
C10 102 0 39F
** NODE: 102 = nand2_3/A
VCC 1 0 5

VIN1 126 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )
+ DC 0

VIN2 116 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )
+ DC 0

.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 750NSEC
.END