** SPICE file created for circuit nor2
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 44.5
RLUMP1 102 103 211.0
RLUMP2 104 105 58.0
M0 101 103 105 1 pfet L=2.0U W=4.0U
RLUMP3 106 107 211.0
RLUMP4 100 108 44.5
M1 1 107 108 1 pfet L=2.0U W=4.0U
RLUMP5 104 109 58.0
RLUMP6 102 110 211.0
M2 109 110 0 0 nfet L=2.0U W=4.0U
RLUMP7 106 111 211.0
RLUMP8 104 112 58.0
M3 0 111 112 0 nfet L=2.0U W=4.0U
** NODE: 0 = GND!
C0 1 0 14F
** NODE: 1 = Vdd!
C1 100 0 11F
** NODE: 100 = 8_7_10#
C2 104 0 28F
** NODE: 104 = Z
** NODE: 106 = B
** NODE: 102 = A
VCC 1 0 5

VIN0 106 0 PWL (   0NS 0   50N 0  100N 5  150N 5  200N 0  250N 0  300N 5  350N 5
+                400NS 0  450N 0  500N 5  550N 5  600N 0  650N 0  700N 5  750N 5 )

VIN1 102 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )

**VIN2 ___ 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 0  250NS 0  300NS 0  350NS 0
**+                400NS 5  450NS 5  500NS 5  550NS 5  600NS 5  650NS 5  700NS 5  750NS 5 )

.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 750NSEC
.END