** SPICE file created for circuit nand3
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 211.0
RLUMP1 102 103 197.5
M0 1 101 103 1 pfet L=2.0U W=4.0U
RLUMP2 102 104 197.5
RLUMP3 105 106 211.0
M1 104 106 1 1 pfet L=2.0U W=4.0U
RLUMP4 107 108 211.0
RLUMP5 102 109 197.5
M2 1 108 109 1 pfet L=2.0U W=4.0U
RLUMP6 110 111 20.5
RLUMP7 100 112 211.0
RLUMP8 102 113 197.5
M3 111 112 113 0 nfet L=2.0U W=4.0U
RLUMP9 114 115 20.5
RLUMP10 105 116 211.0
RLUMP11 110 117 20.5
M4 115 116 117 0 nfet L=2.0U W=4.0U
RLUMP12 107 118 211.0
RLUMP13 114 119 20.5
M5 0 118 119 0 nfet L=2.0U W=4.0U
** NODE: 0 = GND!
C0 114 0 12F
** NODE: 114 = 8_33_19#
C1 110 0 12F
** NODE: 110 = 8_49_19#
C2 1 0 26F
** NODE: 1 = Vdd!
C3 102 0 41F
** NODE: 102 = Z
** NODE: 107 = C
** NODE: 105 = B
** NODE: 100 = A
VCC 1 0 5

VIN0 107 0 PWL (   0NS 0   50N 0  100N 5  150N 5  200N 0  250N 0  300N 5  350N 5
+                400NS 0  450N 0  500N 5  550N 5  600N 0  650N 0  700N 5  750N 5 )

VIN1 105 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )

VIN2 100 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 0  250NS 0  300NS 0  350NS 0
+                400NS 5  450NS 5  500NS 5  550NS 5  600NS 5  650NS 5  700NS 5  750NS 5 )

.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 750NSEC
.END