** SPICE file created for circuit mux_4to1
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 714.5
RLUMP1 102 103 601.5
M0 1 101 103 1 pfet L=2.0U W=4.0U
RLUMP2 102 104 601.5
RLUMP3 100 105 714.5
M1 104 105 0 0 nfet L=2.0U W=4.0U
RLUMP4 106 107 258.0
RLUMP5 102 108 601.5
RLUMP6 109 110 437.0
M2 107 108 110 1 pfet L=2.0U W=4.0U
RLUMP7 106 111 258.0
RLUMP8 100 112 714.5
RLUMP9 109 113 437.0
M3 111 112 113 0 nfet L=2.0U W=4.0U
RLUMP10 106 114 258.0
RLUMP11 100 115 714.5
RLUMP12 116 117 437.5
M4 114 115 117 1 pfet L=2.0U W=4.0U
RLUMP13 106 118 258.0
RLUMP14 102 119 601.5
RLUMP15 116 120 437.5
M5 118 119 120 0 nfet L=2.0U W=4.0U
RLUMP16 121 122 1611.0
RLUMP17 123 124 601.5
M6 1 122 124 1 pfet L=2.0U W=4.0U
RLUMP18 123 125 601.5
RLUMP19 121 126 1611.0
M7 125 126 0 0 nfet L=2.0U W=4.0U
RLUMP20 109 127 437.0
RLUMP21 123 128 601.5
RLUMP22 129 130 54.5
M8 127 128 130 1 pfet L=2.0U W=4.0U
RLUMP23 109 131 437.0
RLUMP24 121 132 1611.0
RLUMP25 129 133 54.5
M9 131 132 133 0 nfet L=2.0U W=4.0U
RLUMP26 109 134 437.0
RLUMP27 121 135 1611.0
RLUMP28 136 137 54.5
M10 134 135 137 1 pfet L=2.0U W=4.0U
RLUMP29 109 138 437.0
RLUMP30 123 139 601.5
RLUMP31 136 140 54.5
M11 138 139 140 0 nfet L=2.0U W=4.0U
RLUMP32 121 141 1611.0
RLUMP33 142 143 601.5
M12 1 141 143 1 pfet L=2.0U W=4.0U
RLUMP34 142 144 601.5
RLUMP35 121 145 1611.0
M13 144 145 0 0 nfet L=2.0U W=4.0U
RLUMP36 116 146 437.5
RLUMP37 142 147 601.5
RLUMP38 148 149 54.5
M14 146 147 149 1 pfet L=2.0U W=4.0U
RLUMP39 116 150 437.5
RLUMP40 121 151 1611.0
RLUMP41 148 152 54.5
M15 150 151 152 0 nfet L=2.0U W=4.0U
RLUMP42 116 153 437.5
RLUMP43 121 154 1611.0
RLUMP44 155 156 54.5
M16 153 154 156 1 pfet L=2.0U W=4.0U
RLUMP45 116 157 437.5
RLUMP46 142 158 601.5
RLUMP47 155 159 54.5
M17 157 158 159 0 nfet L=2.0U W=4.0U
C0 155 0 31F
** NODE: 155 = A0
C1 148 0 28F
** NODE: 148 = A1
C2 142 0 55F
** NODE: 142 = mux_2to1_0/~A
C3 136 0 31F
** NODE: 136 = A2
C4 129 0 28F
** NODE: 129 = A3
C5 123 0 55F
** NODE: 123 = mux_2to1_1/~A
C6 121 0 60F
** NODE: 121 = B0
C7 116 0 88F
** NODE: 116 = 9_86_84#
C8 106 0 60F
** NODE: 106 = Z
C9 109 0 79F
** NODE: 109 = 9_104_140#
** NODE: 0 = GND!
C10 102 0 55F
** NODE: 102 = mux_2to1_2/~A
C11 1 0 58F
** NODE: 1 = Vdd!
C12 100 0 26F
** NODE: 100 = B1
VCC 1 0 5

VIN0 121 0 PWL (   0NS 0   50N 0  100N 5  150N 5  200N 0  250N 0  300N 5  350N 5
+                400NS 0  450N 0  500N 5  550N 5  600N 0  650N 0  700N 5  750N 5 )

VIN1 100 0 PWL (   0NS 0   50NS 0  100NS 0  150NS 0  200NS 5  250NS 5  300NS 5  350NS 5
+                400NS 0  450NS 0  500NS 0  550NS 0  600NS 5  650NS 5  700NS 5  750SN 5 )

VA0 155 0 1
VA1 148 0 2
VA2 136 0 3
VA3 129 0 4

.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 750NSEC
.END