** SPICE file created for circuit inv3
** Technology: scmos
**

** NODE: 0 = GND
** NODE: 1 = Vdd
** NODE: 2 = Error
RLUMP0 100 101 187.0
RLUMP1 102 103 92.5
M0 1 101 103 1 pfet L=5.0U W=17.0U
RLUMP2 102 104 92.5
RLUMP3 100 105 187.0
M1 104 105 0 0 nfet L=5.0U W=17.0U
** NODE: 0 = GND!
C0 102 0 101F
** NODE: 102 = Z
C1 100 0 24F
** NODE: 100 = A
C2 1 0 49F
** NODE: 1 = Vdd!
** SPICE file created for circuit inv2
** Technology: scmos
**

VCC 1 0 5
VIN 100 0 PWL (0 0 50NSEC 0 70NSEC 5 120NSEC 5 140NSEC 0 190NSEC 0)
.MODEL pfet PMOS
.MODEL nfet NMOS
.TRAN 1NSEC 200NSEC 0
.END